Integrated circuits are fabricated with a plurality of circuits distributed across a chip, or die. The distributed circuits are electrically connected using conductive interconnect networks. For simplicity, these conductive interconnects are referred to herein as wires. It will be understood, however, that the electrical interconnects are conductive or semiconductor material fabricated as traces having a length, width and thickness. The physical dimensions, layout and material composition dictate the electrical characteristics of the interconnect. That is, for a given material the physical dimensions dictate the resistance of the conductive trace, its electrical current capacity and its capacitance. Integrated circuit designers are faced with the challenge of minimizing signal delay experienced as a voltage signal propagates along the interconnect network. Computer aided tools and algorithms have been developed to assist in determining interconnect physical dimensions to improve time critical networks. For example, see J. Cong, K. S. Leung, Optimal Wiresizing Under Elmore Delay Model, IEEE Transactions on Computer-Aided Design of Circuits and Systems, March 1995, pp. 321-336, for a description of an algorithm which can be used to determine optimal wire widths using tapering techniques to improve timing characteristics.
Wire tapering is a design technique in which wires which are close to a driver circuit are made wider than wires which are close to receiver circuits. This reduces the capacitance of the signal path and increases the spacing between adjacent wires, effectively reducing interconnect delay, power consumption and cross talk in integrated circuits.
Electromigration and self-heating phenomena place constraints on the minimum allowed width of a wire, depending on the current flow through the wire. In academic and commercial tapering solutions, these phenomena are not accounted for. The solutions produced using these techniques result in wires which must be widened by manually editing the resultant design. If this manual editing is not performed, an integrated circuit may be fabricated which has reliability problems. That is, a fuse-type conductor will be created if a wire width is selected which is not sufficient to carry a required current. Over the life of the integrated circuit, therefore, the conductor may fail.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a tool which allows circuit designers to determine optimal interconnect network configurations without compromising a reliability of the integrated circuit.